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EM250
Table 25. SC2 SPI Slave Formats
SC2_SPICFG
Frame Format
2
0
0
0
0
SC2-4S
mode
nSSEL
MSCLK in
2
2
2
0
0
0
0
0
0
0
1
1
1
0
1
SC2-4S
mode
SC2-4S
mode
SC2-4S
mode
MOSI in
MISO out
nSSEL
MSCLK in
MOSI in
MISO out
nSSEL
MSCLK in
MOSI in
MISO out
nSSEL
MSCLK in
MOSI in
MISO out
RX[7]
TX[7]
RX[7]
TX[7]
RX[7]
TX[7]
RX[7]
TX[7]
RX[6]
TX[6]
RX[6]
TX[6]
RX[6]
TX[6]
RX[6]
TX[6]
RX[5]
TX[5]
RX[5]
TX[5]
RX[5]
TX[5]
RX[5]
TX[5]
RX[4]
TX[4]
RX[4]
TX[4]
RX[4]
TX[4]
RX[4]
TX[4]
RX[3]
TX[3]
RX[3]
TX[3]
RX[3]
TX[3]
RX[3]
TX[3]
RX[2]
TX[2]
RX[2]
TX[2]
RX[2]
TX[2]
RX[2]
TX[2]
RX[1]
TX[1]
RX[1]
TX[1]
RX[1]
TX[1]
RX[1]
TX[1]
RX[0]
TX[0]
RX[0]
TX[0]
RX[0]
TX[0]
RX[0]
TX[0]
2
2
0
0
1
-
-
-
-
-
SC2-4S
mode
SC2-3M
Same as above except LSB first instead of MSB first
Illegal
mode
2
0
-
-
-
SC2-2 mode
Illegal
When the slave select (nSSEL) signal is asserted (by the Master), SC2 SPI transmit data is driven to the output
pin MISO and SC2 SPI data is received from the input pin MOSI. When the slave select (nSSEL) signal is
deasserted (by the Master), no data is transferred on the MISO or MOSI pins and the output pin MISO is tri-
stated. The slave select signal nSSEL is used to enable driving the serialized data output signal MISO. It is also
used to reset the SC2 SPI slave shift register.
Characters received and transmitted are passed through receive and transmit FIFOs. The transmit and receive
FIFOs are 4 bytes deep. These FIFOs are accessed under software control by accessing the SC2_DATA data
register or under hardware control using a DMA controller.
Any character received is stored in the (empty) receive FIFO. The register bit SC_SPIRXVAL in the
SC2_SPISTAT register is set to indicate that not all received characters are read out from receive FIFO. If
software or DMA is not reading from the receive FIFO, the receive FIFO will store up to 4 characters. Any
further reception is dropped, and the register bit SC_SPIRXOVF in the SC2_SPISTAT register is set. The RX
FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error
condition until the RX FIFO is drained. Once the DMA marks a RX error, there are two conditions that will clear
the error indication: setting the appropriate SC_TX/RXDMARST bit in the SC2_DMACTRL register, or loading the
appropriate DMA buffer after it has unloaded.
120-0082-000V Rev 1.1
Page 64
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